Snapper
From Albatross
Features:
For more information, see http://www.bluewatersys.com/snapper/
See also: FPGA
| Specifications | |
|---|---|
| Microcontroller | Intel Xscale at 400 MHz |
| Memory | 64MB SDRAM, 1MB Boot Flash, 512MB Flash via xD socket |
| FPGA | Altera Cyclone EP1C4 (400k logic elements) |
| Ethernet | 10/100 MBit |
| USB | 1 x USB 1.1 Device, 2 x USB Host |
| User I/O | 33 CPU, up to 123 FPGA |
| UARTS | 4 total (2 special function) |
| LCD | support up to 800 x 600, 16bit |
| Touchscreen | Philips touchscreen ADC |
| ADC input | 4-channel |
| Audio | Philips stereo codec (2 line in, 2 line out) |
| PCMCIA | Support for upto 2 slots |
| Memory Card | SD Card, MMC Card |
| Serial Buses | SPI, SSP |
| Power | 3.3V 425mA (1400 mW) |
| Board Size | 70mm x 40mm x 12mm mated |
Connection to Other Sytems
Snapper communicates with the other subsystems over serial and parallel communications busses. The serial busses include I2C, SPI and RS232, while the parallel busses include the FPGA interface, and GPIO pins (through the Expansion connector).
I2C is used exclusively for communication with the supervisor. For a greater description of the I2C communications protocol see (FIXME: I2C Protocol Specification).
SPI is used for communication with all the sensors, directly or via SPI ADC's. SPI bus master hardware is to be implemented in the FPGA.
The PXA255 CPU is equipped with four hardware serial ports with varying degrees of functionality (as far as flow control is concerned).
- FFUART supports hardware flow control, and is designated for the Linux console interface. There will be a bash prompt on this port for debugging, and kernel messages (printk()) will be shown on this port. This is the main debugging interface, where programs can be tested interactively through a serial port terminal program, just as on any other Linux box with a terminal. Telnet will be available for other virtual terminals.
- BTUART (supports hardware flow control) is for use by the Communications Radio. Flow control is necessary for this interface because the radio only has a fixed, 64 byte (??) buffer, which may fill rapidly if transmission is interrupted due to external interference.
- IRUART (no flow control) is attached to the GPS receiver. The lack of flow control is not a problem because the GPS receiver does not support flow control either.
- HWUART (supports flow control) is bought all the way out through the wiring loom where it may be connected to external periphials in the plane (such as a cellphone or satellite radio) or used as another debug terminal.
The parallel communication interfaces the FPGA to the CPU, memory mapping the FPGA into the PXA255's address space. The FPGA can then be accessed at the 100MHz memory bus speed from the PXA255.
The PXA255 can also mount a MMC card, and it is envisioned that for cost reasons, this is used as the file system, instead og the more expensive XD cards currently used. Also, by removing the XD card support it frees considerable space on the FPAG. For more information on MMC support for arm-linux on the PXA255 see here.
